1. Field
Embodiments of the present invention relate to a wiring substrate and a manufacturing method thereof, more specifically, relates to a wiring substrate including a core substrate which has a conductive property, and a manufacturing method thereof.
2. Description of Related Art
In recent years, a miniaturization, a slimming down, and a higher performance has been demanded of an electronic instrument such as a mobile communication instrument and, along with this, there has been a demand for a miniaturization and a multilayering of an electronic part, such as a semi-conductor element provided in an electronic instrument, and of a wiring substrate (a package substrate) such as a printed circuit board, and for a high density mounting of an electronic part. In order to meet these kinds of demand, as a mounting method of a semi-conductor element wiring substrate, a bare chip mounting technique, such as a flip chip mounting, which directly mounts a semi-conductor element on a wiring substrate, is being employed.
Also, along with a development of a multi-pin semi-conductor element, a multilayer wiring substrate including multiple wiring layers is being employed as the heretofore described wiring substrate. Furthermore, multiple wiring layers are also essential in a tester board for testing a semi-conductor element. As such a multilayer wiring substrate, for example, a built up multilayer wiring substrate including a micro wiring, in which insulating layers and conductive layers are alternately laminated, formed on one main surface or both main surfaces of a core substrate, is being employed.
In this kind of situation, there is a danger that a device having the heretofore described mounting structure, that is, a semi-conductor device including a semi-conductor element bare chip mounted on a built up multilayer wiring substrate, will have a problem with discrepancies in a heat expansion coefficient between various parts configuring the semi-conductor device, leading to a fatigue breakdown, a disconnection or the like. For example, in a case of using a glass epoxy resin substrate as the built up multilayer wiring substrate, a heat expansion coefficient thereof is about 12 to about 20 ppm/° C. As opposed to this, in a case of the semi-conductor element being made of silicon (Si), a heat expansion coefficient thereof is approximately 3.5 ppm/° C. That is, the heat expansion coefficient of the wiring substrate and the heat expansion coefficient of the semi-conductor element differ at least significantly, if not greatly. Consequently, in a case of a temperature change occurring, there is a danger that there will be a problem with a thermal stress, a thermal strain or the like, due to such a heat expansion coefficient difference, leading to a fatigue breakdown, a disconnection or the like.
In order to respond to such a problem, an aspect has been proposed wherein the heat expansion coefficient of the wiring substrate on which the semi-conductor element is to be mounted is reduced, making the difference between the heat expansion coefficient of the semi-conductor element and wiring substrate smaller. Specifically, a wiring substrate has been proposed which, in place of a glass cloth used as the base material (the core substrate) of the glass epoxy resin substrate, employs a resin using a carbon fiber material, of which a heat expansion coefficient is approximately 1.0 to approximately 20 ppm/° C., as the base material (the core substrate).
As one example of the heretofore described wiring substrate, for example, a wiring substrate has been proposed which uses a wiring substrate base material wherein a carbon cloth is impregnated with an epoxy resin. In the example, by providing resin holes in the wiring substrate base material, and loading the epoxy resin into the resin holes, wiring layers are formed on the wiring substrate base material. Then, providing through holes connecting the wiring layers, center lines of the resin holes and center lines of the through holes are caused to approximately coincide.
Also, an electronic part has been proposed wherein, an insulating resin layer being provided on at least one portion of a conductive layer formed on the substrate, the insulating resin layer is formed using an electrodeposition method.
Furthermore, a wiring substrate has been proposed wherein, at least one conductive layer being formed on the substrate, an insulating resin layer is formed, using an electrodeposition method, between the substrate and the conductive layer. In the example, the electrodeposited film includes an organic solvent soluble polyimide and a hydrophilic polymer.
Furthermore, a circuit substrate has been proposed wherein a columnar conductor is disposed in a through hole of a fiber reinforced resin substrate. In the example, a hardened resin layer is interposed between an interior wall surface of the through hole and a peripheral surface of the columnar conductor, and an upper surface of the columnar conductor is covered with a conductive thin layer.
Furthermore, a multilayer printed wiring substrate has been proposed which uses a glass fiber woven fabric as a core material reinforcement material. In the example, a material wherein a glass fiber woven fabric is impregnated with a resin (a resin fiber woven fabric) is used as a reinforcement material of a prepreg in which the core material is laminated and bonded together.
Furthermore, a silicon semi-conductor substrate has been proposed wherein, a metal film being provided on an edge portion of a through hole formed in the silicon semi-conductor substrate, an electrodeposited film is formed on an interior surface of the through hole, including the edge portion.
As a density of a semi-conductor element mounted on a wiring substrate increases, a higher density is also demanded for the wiring substrate. Consequently, a miniaturization and a pitch reduction of wiring in the wiring substrate has become indispensable. For this reason, a pitch reduction of not only the wiring but also of through holes formed in a core substrate is required.
In the current situation, there is a problem in that, in a wiring substrate including a core substrate which has a conductive property, as well as not being possible to reliably isolate the core substrate and a conductive layer formed in a through hole, it is not possible to realize a through hole pitch reduction.